FIG. 13 shows the structure of a conventional clock and data recovery circuit. From a reference clock (Ref CLK), multi-phase clocks (multiphase outputs), having an equally-spaced phase difference are generated by a voltage controlled oscillator (VCO) 51 of a phase locked loop (PLL). The VCO 51 is comprised of a ring oscillator of an analog circuit configuration, made up of an odd number of inverter circuits, connected in a ring topology. Multi-phase clocks with an equally spaced phase difference are output in a differential mode from differential inverter circuits of the respective stages making up the ring oscillator. An input data DATA is provided in common to data terminals of plural flip-flops 52 (F/F1 to F/F8) and respective multi-phase clock output from the VCO 51 are fed to clock terminals of the flip-flops 52 (F/F1 to F/F8) which sample the data DATA with rising or falling edges of clock signals and output the sampled data. The clock and data recovery circuit also includes a counter 53 which receives output data output from the plural flip-flops 52 (F/F1 to F/F8) to count up and down logic values of the output data, and a filter 55 which time-averages the output of the counter 53 over a preset time constant. An output voltage of the filter 55 is fed to the voltage-controlled oscillator (VCO) as its control voltage. Part or all of the outputs of the flip-flops 52 and one-phase clock output from the VCO 51 are output as data and clocks, respectively. The outputs of the plural flip-flops 52 (F/F1 to F/F8) are obtained on sampling the data DATA with clocks having phases shifted by a equal value and a sampling waveform which is equivalent to that of sampling the data with a frequency equal to eight times the frequency of the reference clock, is obtained, with the clock timing of a flip-flop, an output value of which does not coincide with the output value of the neighboring flip-flop representing a transition point of the data DATA.
If a clock has a delay with respect to the data transition point, that is if the latch timing is delayed, the count value of the counter 53 is incremented to advance the clock phase, whereas, if the clock leads with respect to the data transition point, the count value of the counter 53 is decremented to delay the clock phase with respect to the data transition point. Meanwhile, the counter 53 may be made up of a charge pump (CP) which charges a capacitor with constant current when the output values of the plural flip-flops 52 (F/F1 to F/F8) are of logic 0 and discharges the capacitor with the constant current when output values of the plural flip-flops 52 (F/F1 to F/F8) are of logic 1.
As a clock and data recovery circuit shown in FIG. 13, reference may be made to Publication 1 (ISSCC 1997 pp. 238 to 239 Alan Fiedler, “A. 1.0625 GHz Tranceiver with 2×—Oversampling and Transmit Signal Preemphasis”). The clock and data recovery circuit, disclosed in the Publication 1, includes a receiver circuit which recovers clocks and data from serial input data to output the recovered clocks and data as parallel data. The VCO (voltage controlled oscillator) of the PLL (phase locked loop) includes a ring oscillator having ten delay stages (10-delay-stage), and 20 clock phases of the VCO provides 2× oversampling clocks to the receiver circuit recovering the clocks and data. The receiver circuit makes the VCO to be locked in input data to recover clocks from the transition of data of NRZ (non-return-to-zero) waveform. Meanwhile, in the clock and data recovery circuit, disclosed in the Publication 1, a data phase detector is made up of a plural number of high-speed latches, and an exclusive-OR logic gate for detecting coincidence/non-coincidence of the high-speed latches. The latch for sampling data bits is clocked with a positive-phase clock of the VCO, while the latch for sampling the boundary between data bits is clocked with a reverse-phase clock of the VCO.
FIG. 14 shows a schematic view of a structure of a clock control circuit, comprised of the combination of a DLL (delay synchronization loop) and an interpolator, as disclosed in Publication 2 (ISSCC 1997 p.p. 332 to 333, S. Sidiropoulos and Mark Horowitz et al., “A semi-digital delay locked loop with unlimited phase shift capability and 0.08–400 MHz operating range”). Referring to FIG. 14, a DLL circuit 60 outputs multi-phase clocks P1 to Pn, synchronized with an input clock. These multi-phase clocks P1 to Pn are fed to a switch 20. Two neighboring signals, selected by the switch 20, are fed to the interpolator (phase interpolator) 30. A signal corresponding to the interior division of the input two signals by the interpolator 30 is output at an output OUT. A control circuit 40 variably controls the interior division ratio of the interpolator 30, based on the result of detection of the phase difference between the output OUT and the reference clock, while controlling the switching of the switch 20.
The interpolator 30 (phase interpolator) of FIG. 14 is made up of an analog circuit shown in FIG. 15. Referring to FIG. 15, this phase interpolator includes N-channel MOS transistors MN61, and MN62, forming a first differential pair, the sources of which are connected in common to a first constant current source CS1, the gates of which receive differentially clocks IN1 and IN1B, outputs pair of which are connected to one end of a first load (a common drain of P-channel MOS transistors MP6l and MP62 connected in parallel) and to one end of a second load (a common drain of P-channel MOS transistors MP63 and MP64 connected in parallel). The phase interpolator also includes N-channel MOS transistors MN63, and MN64, forming a second differential pair, the sources of which are connected in common to a second constant current source CS2, the gates of which receive differentially clocks IN2 and IN2B, outputs pair of which are connected to one end of a first load (a common drain of P-channel MOS transistors MP61 and MP62 connected in parallel) and to one end of a second load (a common drain of P-channel MOS transistors MP63 and MP64 connected in parallel). From the outputs pairs connected in common of the first and second differential pairs are output signals OUT and OUTB having the phases of the weighted sum of the two input clocks. In this phase interpolator, digital weight codes ict1 (16 bits of b[0] to b[15]) are fed to first and second constant current sources CS1 and CS2 to vary the current values of the first and second constant current sources CS1 and CS2, for conversion to the phase of the output clock. That is, the number of the constant current source transistors MN6B.sub.1 to MN6B.sub. 15 is selected by the turning on/off of the N-channel MOS transistors MN6A.sub. 1 to MN6A.sub.15, the gate terminals of which receive 16 bits b[0] to b[15], respectively, to vary the current value.
On the other hand, Publication 3 (155CC 1999 p.p. 180 to 181 “A2BParallel 1.25 Gb/s Interconnect I/O interface with Self Configurable Link and Plesiochronous Clocking”) discloses a configuration, shown in FIG. 16, as a phase interpolator. Referring to FIG. 16, an output current of a current output type configuration which outputs an output current proportionate to the control circuit Ict1 is mirrored by a first current mirror circuit (MN74, and MN75), and the mirrored current is received by a second current mirror circuit (MN73, and MN74), an output mirror current of which is fed to a differential pair circuit which receives as inputs the differential clock inputs IN, and INB. The differential pair circuit is provided with the current from the constant current source transistor MN73 forming the second output end of the first current mirror circuit (MN74, and MN75) and clocks OUT, and OUTB, corresponding to phase shifted versions of the clocks IN, are output at the output nodes of the differential pair circuit. Meanwhile, the differential pair circuit includes N-channel MOS transistors MN71, and MN72, the sources of which are connected in common to a constant current source transistor MP73 and the gates of which are fed with differential clock pairs IN, and INB, and P-channel MOS transistors MP71, and MP72, the sources of which are connected in common to the drain of an output transistor MP74 of the second current mirror circuit, the gates of which are fed with differential clocks IN, and INB and the drains of which are connected to the drains of the N-channel MOS transistors MN71, and MN72. Outputs OUT, and OUTB are taken at the drains of the of the N-channel MOS transistors MN71, and MN72. Connecting the drains of the N-channel MOS transistors MN71, and MN72 and ground are capacitances Cl, and C2, respectively, whereas, between the drains of the N-channel MOS transistors MN71, and MN72, transistors N-channel MOS transistors MN76 and MN77 are connected in series with each other. When the N-channel MOS transistors MN76 and MN77 are turned on, the outputs OUT, and OUTB are charged to an intermediate potential VDD.
In FIG. 16, when the clock IN makes a transition to a high level, the N-channel MOS transistor MN71 is turned on to turn the N-channel MOS transistor MN72 and the P-channel MOS transistor MN71 off and on, respectively to discharge the capacitor C1 while charging the capacitor C2 with the outputs OUT and OUTB making transitions to a low and high level, respectively. When the clock IN makes a transition to a low level, the N-channel MOS transistor MN71 is turned off to turn the N-channel MOS transistor MN72 and the P-channel MOS transistor MP72 on and off, respectively to charge the capacitor C1, while discharging the capacitor C2, with the outputs OUT and OUTB making transitions to a high and low level, respectively. So, the clock frequency band is variably controlled by the control signal Ict1 supplied to the digital analog converter (DAC).
As explained with reference to FIGS. 13 and 15, the above-described conventional circuit generates multi-phase clocks by the VCO circuit and, as an interpolator, a phase interpolator comprised of an analog circuit is adopted.
Moreover, as shown in FIG. 16, the analog phase interpolator has its band control being performed by the current which flows into the current source, such that, if a plural number of frequency bands are to be dealt with, such measures as widening the output current range of the constant current source is needed. In such case, it is not necessarily easy to compensate the linearity of the phase interpolator to enlarge the output current range of the constant current source.